Design & Implementation of Instruction List (IL) Processor on FPGA Platform Project is a VHDL Based FPGA Project for Final Year electronics and communication students. Detailed explanation of block diagram and results are given in project report.
There are three functional units separated by the pipeline registers.
- An Instruction is fetched from the fetch unit and decoded by decode unit to
interpret how is it to be executed.
- Decode unit then generates some signals which are further used by execution unit
to carry out the execution of the instruction.
- Pipeline registers isolate the functional units while bringing simultaneity in their
operation i.e. all functional blocks are working in parallel on different instructions.
In conclusion, we can say that the work in this project proposes development of a PLC application specific Instruction List processor, for smaller response time during safety and speed critical operations. This processor is ported on FPGA to get high speed at low power consumption.
The instruction set of proposed IL processor is dedicated to PLC operations. Also, a three stage instruction pipeline is employed so that execution speed is boosted-up and the PLC can responds to the fast changing inputs in high speed applications. The drawback of the instruction pipeline, the pipeline hazard, is avoided through some design considerations while designing the processor. Also, Xilinx DCM technology is used which gives a true single cycle execution.
The proposed IL processor can be further enhanced with some more PLC dedicated instructions which give more features and yield small size PLC programs. By doing this, application area can be further increased. The IL program for the proposed processor needs to be manually written in machine language. This may introduce errors in the program. In future, an IL assembler can be designed so that IL program can be input as sequence of instructions in medium level language.